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1 ds05-11212-1e fujitsu semiconductor data sheet memory cmos 1m 32 bit hyper page mode dram module mb85343c-60/-70 cmos 1,048,576 32 bit hyper page mode dram module n description the fujitsu mb85343c is a fully decoded, cmos dynamic random access memory (dram) module consisting of eight mb814405c devices. the mb85343c is optimized for those applications requiring high speed, high performance and large memory storage. the operation and electrical characteristics of the mb85343c are the same as the mb814405c which features hyper page mode operation providing extended valid time for data output and higher speed random access of upto 1,024 32bits of data within the same row than the fast page mode. for ease of memory expansion, the mb85343c is offered in a 72-pad single in-line memory module package (simm). n absolute maximum ratings (see note.) note: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol value unit supply voltage v cc ?.5 to +7.0 v input voltage v in ?.5 to +7.0 v output voltage v out ?.5 to +7.0 v short circuit output current i out 50 ma power dissipation p d 8w storage temperature t stg ?5 to +125 c this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
2 mb85343c-60/MB85343C-70 n product line & features parameter mb85343c-60 MB85343C-70 ras access time 60 ns max. 70 ns max. random cycle time 104 ns min. 119 ns min. address access time 30 ns max. 35 ns max. cas access time 15 ns max. 20 ns max. hyper page mode cycle time 25 ns min. 30 ns min. power dissipation operating mode 2688 mw max. 2376 mw max. hyper page mode 2904 mw max. 2424 mw max. standby mode 88 mw max. 88 mw max. self refresh mode 44 mw max. 44 mw max. msp-72p-p48 n pin assignment 67 68 69 70 pin # symbol pd1 pd2 pd3 pd4 -60 -70 nc nc nc nc organization: 1,048,576 words 32 bits memory : mb814405c, 8 pcs decoupling capacitor, 8 pcs 5.0 v 10% supply voltage 1,024 refresh cycles/16.4 ms hyper page mode operation (edo) mss-72p-p29 n package package and ordering information: 72-pad simm, order as mb85343c?xpjpbk (pjpbk = gold pad) mb85343c?xpjpb (pjpb = solder pad) v ss v ss v ss v ss 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 dq0 dq1 dq2 dq3 vcc a0 a2 a4 a6 dq4 dq5 dq6 dq7 a7 vcc a9 ras 2 nc nc cas 0 cas 3 ras 0 nc nc dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 nc pd2 pd4 vss vss dq16 dq17 dq18 dq19 nc a1 a3 a5 nc dq20 dq21 dq22 dq23 nc a8 nc nc nc vss cas 2 cas 1 nc we dq8 dq9 dq10 dq11 dq12 vcc dq13 dq14 dq15 pd1 pd3 nc
3 mb85343c-60/MB85343C-70 functional block diagram cas 0 ras 0 cas 1 cas 3 cas 2 ras 2 we a0 ?a9 v cc v ss c0-7 chips 00-07 chips 00-07 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o i/o i/o i/o a0-a9 chip 00 w cas ras oe i/o i/o i/o i/o a0-a9 chip 01 w cas ras oe i/o i/o i/o i/o a0-a9 chip 02 w cas ras oe i/o i/o i/o i/o a0-a9 chip 03 w cas ras oe i/o i/o i/o i/o a0-a9 chip 04 w cas ras oe i/o i/o i/o i/o a0-a9 chip 06 w cas ras oe i/o i/o i/o i/o a0-a9 chip 07 w cas ras oe i/o i/o i/o i/o a0-a9 chip 05 w cas ras oe
4 mb85343c-60/MB85343C-70 n recommended operating conditions (referenced to v ss ) note: *undershoots of up to ?.0 volts with a pulse width not exceeding 20 ns are acceptable. n dc characteristics (recommended operating conditions unless otherwise noted.) notes: *1 referenced to v ss . *2 i cc depends on the output load conditions and cycle rate. the specific values are obtained with the output open. i cc depends on the number of address change as ras = v il and cas = v ih , v il > ?.3v. i cc1 , i cc3 and i cc5 are specified at one time of address change during ras = v il and cas = v ih . i cc4 is specified at one time of address change during one page cycle. parameter symbol min. typ. max. unit supply voltage v cc 4.5 5.0 5.5 v ground v ss ?v input high voltage, all inputs v ih 2.4 6.5 v input low voltage, all inputs* v il ?.3 0.8 v ambient temperature t a 070 c parameter test condition symbol min. max. unit output high voltage* 1 i oh = ? ma v oh 2.4 v output low voltage* 1 i ol = 4.2 ma v ol 0.4 v input leakage current ras 0 v v in 5.5 v, 4.5 v v cc 5.5 v, v ss = 0 v, all other pins not under test = 0 v i i ( l ) ?0 30 m a cas ?0 20 address, we ?0 60 output leakage current 0 v v out 5.5 v, data out disabled i o( l ) ?0 10 m a operating current* 2 (average power supply current) mb85343c-60 ras & cas cycling, t rc = min. i cc1 488 ma MB85343C-70 432 standby current (power supply current) ttl level ras = cas =v ih i cc2 ?6 ma cmos level ras = cas 3 v cc ?.2 v 8 refresh current #1* 2 (average power supply current) mb85343c-60 cas = v ih , ras = cycling, t rc = min. i cc3 488 ma MB85343C-70 432 hyper page mode current* 2 mb85343c-60 ras = v il , cas = cycling, t hpc = min. i cc4 528 ma MB85343C-70 440 refresh current #2* 2 (average power supply current) mb85343c-60 ras = cycling, cas -before- ras , t rc = min. i cc5 392 ma MB85343C-70 352 refresh current #3 (average power supply current) mb85343c-60 ras = cas 0.2v, self refresh i cc9 ? ma MB85343C-70 8
5 mb85343c-60/MB85343C-70 n capacitance (t a = 25 c, f = 1 mhz) parameter symbol typ. max. unit input capacitance, a0 to a9 c in1 ?1pf input capacitance, ras 0 and ras 2c in2 ?4pf input capacitance, cas 0 to cas 3c in3 ?3pf input capacitance, we c in4 ?5pf i/o capacitance, (dq0-31) c dq ?1pf
6 mb85343c-60/MB85343C-70 n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 1, 2, 3 (continued) no. parameter symbol mb85343c-60 MB85343C-70 unit notes min. max. min. max. 1 time between refresh t ref 16.4 16.4 ms 2 random read/write cycle time t rc 104 119 ns 3 access time from ras t rac ?0?0ns4, 7 4 access time from cas t cac ?5?0ns5, 7 5 column address access time t aa ?0?5ns6, 7 6 output hold time t oh 5?ns 7 output hold time from cas t ohc 5?ns 8 output buffer turn on delay time t on 0?ns 9 output buffer turn off delay time t off ?5?5ns8 10 output buffer turn off delay time from ras t ofr ?5?5ns8 11 transition time t t 150150ns 12 ras precharge time t rp 40?5ns 13 ras pulse width t ras 60 100000 70 100000 ns 14 ras hold time t rsh 15?0ns 15 cas to ras precharge time t crp 0?ns 16 ras to cas delay time t rcd 14 45 14 50 ns 9, 10 17 cas pulse width t cas 10 10000 10 10000 ns 18 cas hold time t csh 40?0ns 19 cas precharge time (normal) t cpn 10?0ns15 20 row address setup time t asr 0?ns 21 row address hold time t rah 10?0ns 22 column address setup time t asc 0?ns 23 column address hold time t cah 10?0ns 24 ras to column address delay time t rad 12 30 12 35 ns 11 25 column address to ras lead time t ral 30?5ns 26 column address to cas lead time t cal 23?8ns 27 read command setup time t rcs 0?ns 28 read command hold time referenced to ras t rrh 0?ns12 29 read command hold time referenced to cas t rch 0?ns12 30 write command setup time t wcs 0?ns13
7 mb85343c-60/MB85343C-70 n ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) notes 1, 2, 3 no. parameter symbol mb85343c-60 MB85343C-70 unit notes min. max. min. max. 31 write command hold time t wch 10?0ns 32 we pulse width t wp 10?0ns 33 write command to ras lead time t rwl 15?8ns 34 write command to cas lead time t cwl 10?0ns 35 din setup time t ds 0?ns 36 din hold time t dh 10?0ns 37 data hold time from ras t dhr 50?5ns 38 ras precharge time to cas active time (refresh cycles) t rpc 5?ns 39 cas setup time (c-b-r refresh) t csr 0?ns 40 cas hold time (c-b-r refresh) t chr 10?0ns 41 we setup time from ras t wsr 0?ns17 42 we hold time from ras t whr 10?0ns17 43 din to cas delay time t dzc 0?ns 44 we to data in delay time t wed 15?5ns 45 ras to data in delay time t rdd 15?5ns 46 cas to data in delay time t cdd 15?5ns 47 ras to column address hold time t ar 26?6ns 48 write command hold time referenced to ras t wcr 24?4ns 49 data input hold time referenced to ras t dhr 24?4ns 50 hyper page mode ras pulse width t rasp 200000 200000 ns 51 hyper page mode read/write cycle time t hpc 25?0ns 52 access time from cas precharge t cpa ?5?0ns7, 14 53 hyper page mode cas precharge time t cp 10?0ns 54 hyper page mode ras hold time from cas precharge t rhcp 35?0ns 55 ras pulse width for self refresh t rass 100 100 m s16 56 ras precharge time for self refresh t rps 104 119 ns 16 57 cas hold time for self refresh t chs ?0 ?0 ns 16
8 mb85343c-60/MB85343C-70 notes: 1. an initial pause (ras =cas =v ih ) of 200 m s is required after power-up followed by any eight ras -only cycles or eight cas -before-ras refresh cycles (we =v ih ) before proper device operation is achieved. if an internal refresh counter is used, a minimum of eight cas -before-ras initialization cycles are required instead of eight ras cycles. 2. ac characteristics assume t t = 2 ns. 3. v ih (min.) and v il (max.) are reference levels for measuring the timing of input signals. transition times are measured between v ih (min.) and v il (max.). 4. assumes that t rcd t rcd (max.), t rad t rad (max.). if t rcd and/or t rad is greater than the maximum recommended value shown in this table, t rac will be increased by the amount that t rcd exceeds the value shown. 5. if t rcd 3 t rcd (max.), t rad 3 t rad (max.), and t asc 3 t aa ?t cac ?t t , access time is t cac . 6. if t rad 3 t rad (max.) and t asc t aa ?t cac ?t t , access time is t aa . 7. measured with a load equivalent to two ttl loads and 100 pf. 8. t off and t ofr are specified that output buffer change to high impedance state. 9. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is speci?d as a reference point only; if t rcd is greater than the speci?d t rcd (max.) limit, access time is controlled exclusively by t cac or t aa . 10. t rcd (min.) = t rah (min.)+ 2 t t + t asc (min.). 11. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is speci?d as a reference point only; if t rad is greater than the speci?d t rad (max.) limit, access time is controlled exclusively by t cac or t aa . 12. either t rrh or t rch must be satis?d for a read cycle. 13. t wcs is speci?d as a reference point only. if t wcs 3 t wcs (min.) the data output pin will remain high-z state through entire cycle. 14. t cpa is access time from the selection of a new column address (caused by changing cas from ??to ??. therefore, if t cp become long, t cpa also become longer than t cpa (max.). 15. assumes that cas -before-ras refresh cycle. 16. assumes that cas -before-ras self refresh cycle. 17. assumes test mode function. *source: see mb814405c data sheet for details on the electricals.
9 mb85343c-60/MB85343C-70 n package dimensions +0.10 C0.08 +.004 C.003 * 1.27 .050 details of "a" part 1.04(.041)typ. 0.25(.010)max. 2.54(.100)min. (?.125.002) ?3.180.05 5.08(.200)min. 5.08(.200)max. (.925.005) 23.500.13 resistor mounting area. (.050.001) 1.270.03 (.250.001) 6.350.03 (r.062.005) r1.570.13 (.250.005) 6.350.13 (.400.003) 10.160.08 (.250.005) 6.350.13 (.080.005) pin no.1 index 2.030.13 (r.062.002) r1.570.05 (1.750.002) 44.450.05 107.950.13(4.250.005) 101.190.10(3.984.004) 95.250.05(3.750.002) "a" 1 1995 fujitsu limited m72030sc-1-2 c 72 pin, plastic simm (mss-72p-p29) dimensions in mm(inches).
10 mb85343c-60/MB85343C-70 n package dimensions +0.15 C0.08 +.006 C.003 * details of "a" part 1.04(.041)typ. 2.54(.100)min. 0.25(.010)max. ? 3.180.05 (? .125.002) 1.27 .050 5.08(.200)min. 5.08(.200)max. 23.500.13 (.925.005) 1.270.03 (.050.001) resistor mounting area. 101.190.10 107.950.13 (4.250.005) (3.984.004) 95.250.05 (3.750.002) "a" 6.350.03 (.250.001) r 1.570.05 (r .062.002) 44.450.05 (1.750.002) r 1.570.05 (r .062.002) 2.030.13 (.080.005) 6.350.13 (.250.005) pin no.1 index 6.350.13 10.160.08 (.400.003) (.250.005) 1 1995 fujitsu limited m72049sc-1-2 c 72 pin, plastic simm (mss-72p-p48) dimensions in mm(inches).
24 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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